The present invention relates generally to decode time instruction optimization, and more specifically, to optimization for load reserve and store conditional sequences.
In the Power ISA®, the load reserve function is implemented by the Load Word and Reserve Indexed (lwarx) and the store conditional function is implemented by the Store Double Word Conditional Indexed (stwcx). The stwcx and lwarx instructions are primitive, or simple, instructions used to perform a read-modify-write operation to storage. If the store is performed responsive to a store conditional, the use of the stwcx and lwarx instructions ensures that no other processor or mechanism has modified the target memory location between the time the lwarx instruction is executed and the time the stwcx instruction completes.
Further information can be found in “Power ISA™ Version 2.06 Revision B” published Jul. 23, 2010 from IBM® herein incorporated by reference in its entirety. In some implementations of the Power ISA®, additional load reserve and store conditional instructions are optionally provided for other data widths.
Additional information can be found in “64-bit PowerPC ELF Application Binary Interface Supplement 1.9” (2004) from IBM® and incorporated by reference herein in its entirety.
Also, information can be found in “Power Architecture® 32-bit Application Binary Interface Supplement 1.0 Linux®” (Apr. 19, 2011) and “Power Architecture® 32-bit Application Binary Interface Supplement 1.0-Embedded” (Apr. 19, 2011), both of which are incorporated by reference herein in their entirety.